Semiconductor processing may frequently include an etch into or through silicon oxide-containing material. The silicon oxide-containing material may be undoped (and thus may consist of silicon dioxide (SiO2)), or may be doped (and thus may comprise, for example, one or more of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), and fluorosilicate glass (FSG)).
An example application in which silicon oxide-containing material is etched is the formation of capacitor container openings. FIGS. 1-3 illustrate a conventional method for forming capacitor container openings within silicon oxide-containing material.
Referring to FIG. 1, such shows a semiconductor construction 10 at a preliminary processing stage. Construction 10 comprises a base semiconductor material 12 having a plurality of transistors 14, 16 and 18 supported thereby. The base semiconductor material may comprise any suitable semiconductor composition or combination of compositions; and may, for example, comprise, consist essentially of or consist of monocrystalline silicon lightly background doped with appropriate dopant. The base may be a portion of a monocrystalline silicon wafer.
The base 12 may be considered to be a semiconductor substrate, or a portion of a semiconductor substrate. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Transistors 14, 16 and 18 comprise gates 24, 26 and 28, respectively. Such gates include stacks comprising gate dielectric 30, electrically conductive gate material 32, and an electrically insulative cap 34. The electrically conductive gate material may comprise one or more of metal (such as titanium or tungsten), metal compounds (for instance, metal silicide or metal nitride), and conductively-doped semiconductor material (for instance, conductively-doped silicon). The gate dielectric may comprise silicon dioxide. The insulative caps may comprise one or more of silicon nitride, silicon dioxide and silicon oxynitride.
Electrically insulative sidewall spacers 36 are along sidewalls of the gates. Such sidewall spacers may one or more of silicon dioxide, silicon nitride and silicon oxynitride.
Transistors 14, 16 and 18 comprise source/drain regions 40, 42, 44, 46 and 48. Transistors 14 and 16 are paired, and share a common source/drain region 42. Transistor 18 may be part of another paired transistor set, so that source/drain region 48 is also a shared source/drain region. Source/drain regions 44 and 46 are electrically isolated from one another by an isolation region 45 provided between them. The isolation region is filled with insulative material, such as, for example, one or both of silicon dioxide and silicon nitride; and may correspond to a shallow trench isolation region.
Ultimately, shared source/drain regions 42 and 48 may be connected to bitlines, and the remaining source/drain regions 40, 44 and 46 may be connected to capacitors. Accordingly, transistors 14, 16 and 18 may be incorporated into a dynamic random access memory (DRAM) array.
A silicon oxide-containing material 50 is over transistors 14, 16 and 18. The silicon oxide-containing material may comprise a single homogeneous mass as shown, or may comprise multiple layers. A majority of the silicon oxide-containing material may consist of one or more of doped oxides, such as BPSG, PSG or FSG; and in some applications an entirety of the silicon oxide-containing material 50 may consist of one or more doped oxides. In some applications, at least a portion of silicon oxide containing material 50 may consist of silicon dioxide. For instance, a lower portion of silicon oxide-containing material 50 may be a layer of silicon dioxide, and the remainder of silicon oxide-containing material 50 may be one or more doped oxides.
A patterned mask 52 is formed over material 50. The patterned mask has a plurality of openings 54, 56 and 58 extending therethrough. The patterned mask may comprise, consist essentially of or consist of carbon-containing material, such as transparent carbon, amorphous carbon and/or photoresist.
Referring to FIG. 2, openings 54, 56 and 58 are extended through silicon oxide-containing material 50 to source/drain regions 40, 44 and 46, respectively. The openings may be extended through the silicon oxide-containing material with an etch utilizing C4F8 (flowed at about 60 standard cubic centimeters per minute (sccm)), argon (flowed at about 1100 sccm), oxygen (flowed at about 25 sccm) and C4F6 (flowed at about 2 sccm). Such etch may be conducted under a pressure of about 30 millitorr, utilizing a plasma power of about 2100 watts at about 60 megahertz, and a substrate bias of about 3500 watts at about 2 megahertz.
A problem with an etch as described above is that it may create the shown bowing within openings 56 and 58, which creates widened regions 60 and 62. Such widened regions thin a sidewall between them so that openings 56 and 68 touch or nearly touch at a location 63. Also, the etch may lead to so-called “twisting” within the openings such that the internal periphery of the openings appears to twist along the vertical length of the openings.
Referring to FIG. 3, masking material 52 (FIG. 2) is removed and capacitor materials 70, 72 and 74 are formed within the openings 54, 56 and 58. Capacitor material 70 is a first electrode material, capacitor material 72 is a dielectric material, and capacitor material 74 is a second electrode material. Materials 70 and 74 are electrically conductive, and may comprise one or more of metal, metal compounds, and conductively-doped semiconductor materials. Material 72 is electrically insulative, and may comprise one or more of silicon dioxide, silicon nitride, and various high-k materials.
Materials 70, 72 and 74 are intended to form capacitor constructions 80, 82 and 84 within openings 54, 56 and 58. Unfortunately, the bowing within openings 56 and 58 may cause capacitors 82 and 84 to be shorted to one another.